A frequency synthesizer may include a phase locked loop (PLL) to derive one of a number of frequencies from a reference frequency, and may be defined in terms of frequency bandwidth, a number of selectable frequencies, spacing between the selectable frequencies, frequency drift, noise/jitter, circuit size, power consumption, and/or jitter.
Jitter may arise from noise, and may be exacerbated at higher operating environment frequencies. Specifically:                [T]he rising demand for high-speed I/O has created an increasingly noisy environment in which DLL's and PLL's must function. This noise, typically in the form of supply and substrate noise, tends to cause the output clocks of DLL's and PLL's to jitter from their ideal timing. With a shrinking tolerance for jitter in the decreasing period of the output clock, the design of low jitter DLL's and PLL's has become very challenging.        Achieving low jitter in PLL and DLL designs can be difficult due to a number of design tradeoffs. Consider a typical PLL which is based on a voltage controlled oscillator (VCO). The amount of input tracking jitter produced as a result of supply and substrate noise is directly related to how quickly the PLL can correct the output frequency. To reduce the jitter, the loop bandwidth should be set as high as possible. Unfortunately, the loop bandwidth is affected by many process technology factors and is constrained to be well below the lowest operating frequency for stability. These constraints can cause the PLL to have a narrow operating frequency range and poor jitter performance.            (J. Maneatis, Low-Jitter Process Independent DLL and PLL Based on Self-Biased Techniques, IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996, page 1723, column 1, citations omitted).
A number of PLL designs have been developed, including inductive-capacitive voltage-controlled oscillator (LC-VCO) based PLLs, and self-biased voltage-controlled oscillator (SB-VCO) based PLLs. An LC-VCO PLL may be suitable to derive a fixed-frequency having relatively little noise or jitter, but may not be suitable to derive a tunable frequency. A SB-VCO PLL may be suitable to derive a tunable frequency, but the frequency may exhibit jitter due to input noise and/or self-generated noise.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.